MX50_ARM2 U-Boot > fatload mmc 2:4 0x70800000 sony_reader/uImage; bootm reading sony_reader/uImage U-Boot 2009.08 (Dec 21 2011 - 14:48:38) CPU: Freescale i.MX50 family 1.1V at 800 MHz mx50 pll1: 800MHz mx50 pll2: 400MHz mx50 pll3: 216MHz ipg clock : 66666666Hz ipg per clock : 66666666Hz uart clock : 24000000Hz ahb clock : 133333333Hz axi_a clock : 400000000Hz axi_b clock : 200000000Hz weim_clock : 100000000Hz ddr clock : 160000000Hz esdhc1 clock : 80000000Hz esdhc2 clock : 80000000Hz esdhc3 clock : 80000000Hz esdhc4 clock : 80000000Hz Board: MX50 ARM2 board Boot Reason: [POR] Boot Device: MMC I2C: ready DRAM: 256 MB MMC: FSL_ESDHC: 0, FSL_ESDHC: 1, FSL_ESDHC: 2 imx_esdhc.c bus_width 0x1 imx_esdhc.c bus_width 0x1 imx_esdhc.c bus_width 0x4 imx_esdhc.c bus_width 0x4 MMC set clock 50MHz imx_esdhc.c bus_width 0x1 imx_esdhc.c bus_width 0x1 imx_esdhc.c bus_width 0x4 imx_esdhc.c bus_width 0x4 MMC set clock 50MHz imx_esdhc.c bus_width 0x1 imx_esdhc.c bus_width 0x1 imx_esdhc.c bus_width 0x4 imx_esdhc.c bus_width 0x4 MMC set clock 50MHz imx_esdhc.c bus_width 0x1 imx_esdhc.c bus_width 0x1 imx_esdhc.c bus_width 0x4 imx_esdhc.c bus_width 0x4 MMC set clock 50MHz temperature 28 imx_esdhc.c bus_width 0x1 imx_esdhc.c bus_width 0x1 imx_esdhc.c bus_width 0x4 imx_esdhc.c bus_width 0x4 MMC set clock 50MHz In: serial Out: serial Err: serial Net: got MAC address from IIM: 00:00:00:00:00:00 FEC0 Hit any key to stop autoboot: 0 MMC read: dev # 0, block # 2048, count 5120 partition # 0 ... imx_esdhc.c bus_width 0x1 imx_esdhc.c bus_width 0x1 imx_esdhc.c bus_width 0x4 imx_esdhc.c bus_width 0x4 SD set clock 50MHz 5120 blocks read: OK MMC read: dev # 0, block # 10240, count 600 partition # 0 ... imx_esdhc.c bus_width 0x1 imx_esdhc.c bus_width 0x1 imx_esdhc.c bus_width 0x4 imx_esdhc.c bus_width 0x4 SD set clock 50MHz 600 blocks read: OK ## Booting kernel from Legacy Image at 70800000 ... Image Name: Normal Kernel Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 2288064 Bytes = 2.2 MB Load Address: 70008000 Entry Point: 70008000 Verifying Checksum ... OK ## Loading init Ramdisk from Legacy Image at 70c00000 ... Image Name: Normal Rootfs Image Type: ARM Linux RAMDisk Image (uncompressed) Data Size: 286848 Bytes = 280.1 kB Load Address: 70308000 Entry Point: 70308000 Verifying Checksum ... OK Loading Kernel Image ... OK OK Starting kernel ... Linux version 2.6.35.3 (hudson@devuntu5) (gcc version 4.4.0 (GCC) ) #1 PREEMPT4 CPU: ARMv7 Processor [412fc085] revision 5 (ARMv7), cr=10c53c7f CPU: VIPT nonaliasing data cache, VIPT nonaliasing instruction cache Machine: Freescale MX50 ARM2 Board Ignoring unrecognised tag 0x54410008 Memory policy: ECC disabled, Data cache writeback Built 1 zonelists in Zone order, mobility grouping on. Total pages: 63754 Kernel command line: console=ttymxc2,115200 init=/init bootdev=0 rawtable=0xF40 PID hash table entries: 1024 (order: 0, 4096 bytes) Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) Memory: 251MB = 251MB total Memory: 249148k/249148k available, 7876k reserved, 0K highmem Virtual kernel memory layout: vector : 0xffff0000 - 0xffff1000 ( 4 kB) fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) DMA : 0xf9e00000 - 0xffe00000 ( 96 MB) vmalloc : 0x90000000 - 0xf4000000 (1600 MB) lowmem : 0x80000000 - 0x8fb00000 ( 251 MB) pkmap : 0x7fe00000 - 0x80000000 ( 2 MB) modules : 0x7f000000 - 0x7fe00000 ( 14 MB) .init : 0x80008000 - 0x80025000 ( 116 kB) .text : 0x80025000 - 0x80424000 (4092 kB) .data : 0x80444000 - 0x804be700 ( 490 kB) SLUB: Genslabs=9, HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 Hierarchical RCU implementation. RCU-based detection of stalled CPUs is disabled. Verbose stalled-CPUs detection is disabled. NR_IRQS:396 MXC GPIO hardware MXC IRQ initialized You should not call the gpmi_set_parent MXC_Early serial console at MMIO 0x63f90000 (options '115200') bootconsole [ttymxc2] enabled Console: colour dummy device 80x30 Mix log static memory : 7fe00000 - 7fffffff address : 90400000 There is not the last log. Initialize a static memory for mix_logger. ##### LOG START ##### Calibrating delay loop... 799.53 BogoMIPS (lpj=3997696) pid_max: default: 32768 minimum: 301 Mount-cache hash table entries: 512 CPU: Testing write buffer coherency: ok regulator: core version 0.5 NET: Registered protocol family 16 i.MX IRAM pool: 128 KB@0x90040000 CPU is i.MX50 Revision 1.1 IR Power is LDO4 This is TPS65181. PWR3DET:power 3 detect FEC disable Using SDMA I.API MXC DMA API initialized IMX usb wakeup probe IMX usb wakeup probe bio: create slab at 0 CSPI: mxc_spi-0 probed CSPI: mxc_spi-2 probed usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb wm831x 0-0034: WM8321 revision C regulator: VCORE: 850 <--> 1100 mV at 1000 mV at 0 uA regulator: VPERI: 950 <--> 1250 mV at 1250 mV at 0 uA regulator: DCDC3: at 1800 mV regulator: DCDC4: at 2900 mV regulator: LDO1: 900 <--> 3300 mV at 1200 mV regulator: LDO2: 900 <--> 3300 mV at 1200 mV regulator: LDO3: 900 <--> 3300 mV at 2500 mV regulator: LDO4: 900 <--> 3300 mV at 3200 mV regulator: LDO5: 900 <--> 3300 mV at 2900 mV regulator: LDO6: 900 <--> 3300 mV at 2500 mV regulator: LDO7: 1000 <--> 3500 mV at 1800 mV regulator: LDO8: 1000 <--> 3500 mV at 2500 mV regulator: LDO9: 1000 <--> 3500 mV at 3100 mV regulator: LDO10: 1000 <--> 3500 mV at 3200 mV regulator: LDO11: 800 <--> 1550 mV at 1200 mV Advanced Linux Sound Architecture Driver Version 1.0.23. Switching to clocksource mxc_timer1 mxsdhci: MXC Secure Digital Host Controller Interface driver mxsdhci: MXC SDHCI Controller Driver. SDHC:sdhci_set_power:slot pwr off mmc_detect_change: id=0 mmc0: SDHCI detect irq 179 irq 1 INTERNAL DMA mxsdhci: MXC SDHCI Controller Driver. SDHC:sdhci_set_power:slot pwr on mmc_detect_change: id=1 mmc1: SDHCI detect irq 0 irq 2 INTERNAL DMA mxsdhci: MXC SDHCI Controller Driver. mmc_detect_change: id=2 mmc2: SDHCI detect irq 228 irq 3 INTERNAL DMA mxsdhci: MXC SDHCI Controller Driver. mmc_detect_change: id=3 mmc3: SDHCI detect irq 0 irq 4 INTERNAL DMA NET: Registered protocol family 2 IP route cache hash table entries: 2048 (order: 1, 8192 bytes) TCP established hash table entries: 8192 (order: 4, 65536 bytes) TCP bind hash table entries: 8192 (order: 3, 32768 bytes) TCP: Hash tables configured (established 8192 bind 8192) TCP reno registered UDP hash table entries: 256 (order: 0, 4096 bytes) UDP-Lite hash table entries: 256 (order: 0, 4096 bytes) NET: Registered protocol family 1 RPC: Registered udp transport module. RPC: Registered tcp transport module. RPC: Registered tcp NFSv4.1 backchannel transport module. Unpacking initramfs... Freeing initrd memory: 280K LPMode driver module loaded Static Power Management for Freescale i.MX5 PM driver module loaded sdram autogating driver module loaded Bus freq driver module loaded mxc_dvfs_core_probe DVFS driver module loaded i.MXC CPU frequency driver DVFS PER driver module loaded ashmem: initialized msgmni has been set to 487 alg: No test for stdrng (krng) cryptodev: driver loaded. io scheduler noop registered io scheduler deadline registered io scheduler cfq registered (default) regulator: DISPLAY: regulator: VCOM: at 1250 mV regulator: V3P3_CTRL: regulator: PMIC_TEMP: regulator: PWR0_CTRL: regulator: PWR2_CTRL: SDHC:sdhci_set_power:slot pwr on regulator: VSYS_EPD: tps65180 1-0048: PMIC TPS6518x for eInk display mmc0: new high speed SDHC card at address e624 mmc_rescan:wake_lock_timeout (0) mmc_rescan:detect done(id=0) mmc2: new high speed MMC card at address 0001 mmc_rescan:wake_lock_timeout (2) mmc_rescan:wifi:wake unlock (3) Serial: MXC Internal UART driver mxcuart register mxcintuart.2: ttymxc2 at MMIO 0x5000c000 (irq = 33) is a Freescale i.MX console [ttymxc2] enabled, bootconsole disabled